View CPC5002G_7815649.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

i ntegrated c ircuits d ivision ds-cpc5002-r01 www.ixysic.com 1 features ? dual optical isolator ? buffers two independent signals ? power-down to hi-z doesn't load outputs ? low-power cmos reduces supply current ? output operates over 2.7v < v dd < 5.5v ? led drive current only 1.5ma ? high speed: 10mbaud typical ? 3750v rms galvanic isolation ? single 8-pin dip or surface mount package applications ? test and measurement ? a/d and d/a isolation ? power converter isolation ? medical ? ground loop elimination ? i 2 c bus isolation ? computer bus isolation ? isolated line receiver approvals ? ul - pending ? en/iec 60950 certified component: tuv certificate: b 11 10 49410 007 description the cpc5002 is a dual hi gh speed optical logic isolator with open-drain outputs providing 3750v rms of galvanic isolation between the inputs and the outputs. activating the input led causes the open-drain output to turn on, pulling the voltage of the external pullup resistor towards ground. utilizing cmos technology enables the output stage?s high-gain circuitry to operate with a miserly power consumption of <5mw (typical) when operated with a 3.3v supply voltage and a low input led drive current of 1.5ma. because optical isolators pa ss logic levels directly there is no internal state refresh clock to maintain a non-changing input. additionally, the cpc5002 will always return the buffered signals to their proper value after a transient interruption at either side. ordering information figure 1. cpc5002 functional block diagram rohs 2002/95/ec e 3 pb part description CPC5002G 8-pin dip (50 / tube) CPC5002Gs 8-pin surface mount (50 / tube) CPC5002Gstr 8-pin surface mount tape & reel (1000 / reel) led led 1 2 3 4 8 7 6 5 v dd out1 out2 gnd a1 k1 k2 a2 dual high-speed open-drain digital optical isolator cpc5002
i ntegrated c ircuits d ivision cpc5002 2 www.ixysic.com r01 1. specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4 esd rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.6 general conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.8 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.9 switching specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.10 propagation delay test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.11 typical switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 power supply decoupling and noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4. circuit examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 inverting and non-inverting configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. manufacturing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 moisture sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 esd sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 board wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.5 mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
i ntegrated c ircuits d ivision cpc5002 r01 www.ixysic.com 3 1 specifications 1.1 package pinout 1.2 pin description 1.3 absolute maximum ratings voltages at output side nodes are with respect to gnd=0v absolute maximum electrical ratings are at 25c. power specifications: no derating required to 85c. absolute maximum ratings are stress rating s. stresses in excess of these ratings c an cause permanent damage to the device. functional operation of the device at condit ions beyond those indicated in the operational sections of this data sheet is not implied. 1.4 esd rating 1 2 3 4 8 7 6 5 pin# name description 1a1 led anode, channel 1 2k1 led cathode, channel 1 3k2 led cathode, channel 2 4a2 led anode, channel 2 5gnd ground, output side supply return 6out2 output, channel 2 7out1 output, channel 1 8 v dd supply voltage, output side parameter symbol rating units forward current continuous i f 20 ma peak 40 led reverse voltage v r 6.5 v supply voltage, output side v dd -0.3 to 6.5 v output voltage v out -0.3 to 6.5 v output current i out 10 ma output power (each output) p out 60 mw isolation voltage (input to output) v iso 3750 v rms operating temperature t a -40 to 85 c operating relative humidity rh 5 to 85 % storage temperature t stg -50 to 125 c esd rating (human body model) 4000v
i ntegrated c ircuits d ivision 4 www.ixysic.com r01 cpc5002 1.5 recommended operating conditions 1.6 general conditions specifications cover the operating temperature range t a = -40c to +85c and supply range v dd = 2.7v to 5.5v. unless otherwise specified, minimum and maximum values are guaranteed by production testing. typical values are the result of engineering evaluations and ar e characteristic of the device at t a = 25c and v dd = 3.3v; they are provided for information purposes only and are not verified by manufacturing testing. 1.7 electrical specifications 1.8 thermal characteristics parameter symbol min typ max units supply voltage v dd 2.7 - 5.5 v led forward current i f 1.4 1.5 10 ma output drive i sink 6ma operating ambient temperature t a -40 +85 c parameter conditions symbol min typ max units input specifications led input threshold current - i th 0.16 0.55 1 ma led forward voltage i f =1.5ma, t a =25c v f 0.98 1.2 1.41 v i f =10ma 1.0 1.3 1.8 led reverse breakdown voltage i r =5 ? av r 6- -v led capacitance v f =0v, f=1mhz c in -50-pf output specifications output drive v dd =2.7v, i sink =3ma v ol - 0.21 0.35 v v dd =2.7v, i sink =6ma -0.420.7 v dd =3.3v, i sink =6ma -0.38- high level leakage current v out =v dd =5.5v i ohl -0.110 ? a supply specifications supply current v dd =3.3v, i sink =0ma i dd -1.4- ma v dd =5.5v, i sink =0ma, t a =25c -2.13 parameter conditions symbol typ units thermal resistance, junction to ambient free air r ? ja 114 c/w led temperature coefficient i f =1.5ma -1.3 mv/c output voltage temperature coefficient i sink =6ma 1.2 mv/c dv f dt --------- - dv out dt ---------------- -
i ntegrated c ircuits d ivision cpc5002 r01 www.ixysic.com 5 1.9 switching specifications 1 falling propagation delay can be reduced by increasing in stantaneous led current drive, typically by increasing c fwd . 2 rising propagation delay depends on r pu , c l , and i f . increasing i f above 2 ? i th (by reducing r s ) increases the rising propagation delay. 3 propagation delay skew is the worst case difference propagation delay, high to low and low to high between the two channels of a cpc5002 when measured using the test circuit sh own below, which is tuned for approxima tely even rising and falling delays. 1.10 propagation delay test circuit parameter conditions symbol min typ max units timing specifications clock frequency i sink =6ma, c l =20pf f max -10-mhz propagation delay output falling 1, 3 i f =1.5ma, v dd =3.3v, r pu =499 ? , c l =20pf, 0.5v in to 0.5v dd_out t phl 35 81 120 ns output rising 2, 3 t plh 35 81 120 pulse width distortion: |t plh - t plh | as per t phl and t plh pwd 85 ns propagation delay skew 3 as per t phl and t plh t psk - - 50 ns output fall time, 90% to 10% i f =1.5ma, v dd =3.3v, r pu =499 ? , c l =20pf t f 10 15 - ns common mode specifications common mode transient immunity v cm =20v p-p , v dd =3.3v, t a =25c v out = high v out >2v cm h 5- - kv/ ? s v out = low v out <0.8v cm l 7- - 2k 27pf 3.3v r pu 499 c l 20pf v dd v out ? cpc5002 i f
i ntegrated c ircuits d ivision 6 www.ixysic.com r01 cpc5002 1.11 typical switching waveforms ty p i c a l @ v dd = 3.3v, i f = 1.5ma, r pu = 499 ? , c l = 20pf v in v out 0 100n 200n 300n 400n 500n time (s) 1.0 0.0 2.0 3.0 4.0 1.0 0.0 2.0 3.0 4.0 (v) (v)
i ntegrated c ircuits d ivision cpc5002 r01 www.ixysic.com 7 2 performance characteristics temperature (oc) -50 -30 -10 10 30 50 70 90 110 led forward volta g e (v) 1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32 led forward volta g e vs. temperature i f =2ma i f =1.5ma led forward current (ma) 01234567 8 910 led forward volta g e (v) 1.19 1.20 1.21 1.22 1.23 1.24 1.25 1.26 1.27 typical led forward volta g e vs. led forward current (t a =25oc) temperature (oc) -50 -30 -10 10 30 50 70 90 110 led current (ma) 0.4 0.5 0.6 0.7 0.8 0.9 1.0 typical led lo g ic threshold current vs. temperature i th_hi i th_hi_typ i th_typ i th_lo_typ i th_lo led current (ma) 1.0 1.5 2.0 2.5 3.0 3.5 delay time (ns) 40 50 60 70 80 90 100 110 delay times vs. led current (c fwd =0pf, v dd =3.3v, r pu =499, c l =20pf) t phl t plh c fwd (pf) 0 5 10 15 20 25 30 delay time (ns) 30 40 50 60 70 80 90 100 110 delay times vs. c feedfwd (i led =1.5ma, v dd =3.3v, r pu =499, c l =20pf) t phl t plh temperature (oc) -50 -30 -10 10 30 50 70 90 110 supply current (ma) 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 typical supply current vs. temperature v dd =5.5v v dd =3.3v v dd =2.7v temperature (oc) -50 -30 -10 10 30 50 70 90 110 v ol (v) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 typical v ol vs. temperature (i sink =6ma) v dd =2.7v v dd =3.3v v dd =5.5v
i ntegrated c ircuits d ivision 8 www.ixysic.com r01 cpc5002 3 functional description 3.1 introduction the cpc5002 provides two independent galvanically isolated high speed open-drain output optical isolators in a single 8-pin package. it ex hibits excellent isolation (3750v rms ) and speed (10mbps typical), and operates over a wide range of supply voltages (2.7v to 5.5v). because the active circuits have been fabricated in a cmos process, the device requires much less supply current (1.4ma typical with v dd = 3.3v) and can run at much lower led currents (1.4ma minimum) than similar devices fabricated with bipolar processes. 3.2 functional description an open-drain output of the cpc5002 will activate and sink current when the light generated by the led and passed across the barrier to the photodetector is sufficient. the minimum level of input current necessary to initiate this behavior is referred to as the led input threshold current (i th ) and is a function of the optical current transfer ratio of the device. to provide consistent performance over the led input threshold current range, the recommended typical led drive current (i f ) over temperature and all operating conditions, is 1.5ma. this recommendation is provided to offer a balance in the propagation delays on both the falling and rising edges of the signal pulse being buffered across the barrier. the absolute value of the mismatch in the delay of these two edges is pulse width distortion. in the specifications these delays are identified as t phl and t plh while the distortion is pwd. in general, choosing a higher led drive current will decrease t phl , the propagation time for the output to go from high to low. this is mostly due to the led generating more light more quickly as it turns on. however, if i f is more than 2 x i th then increasing the led drive current further will cause t plh , the propagation time for the output to go from low to high, to increase. excess levels of i f makes the difference between t plh and t phl (also known as pulse width distortion) greater. pulse width distortion is often of interest when the signal being isolated is a clock. keeping the led drive current near 1.5ma and using the minimum r pu and c l at the output reduces the worst case pulse width distortion and is thus recommended for best waveform fidelity. when using 1.5ma of led drive current and when the cpc5002 is driving a fast output bus (one with minimum r pu and c l ), the average t phl will usually be slightly longer than the average t plh . in this case, reduction of average pulse width distortion can be accomplished by using a small feed forward capacitor. the capacitor boosts the instantaneous current applied to the led at turn-on (reducing t phl ) while leaving the applied dc input current at 1.5ma (t plh unchanged). examples of the feed forward capacitor (c fwd ) are shown in "figure 1. inverting configuration? on page 9 and "figure 2. non-inverting configuration? on page 9 . increasing the value of the feed forward capacitor causes t phl to decrease. for a 499 ? pullup into a 20pf load capacitance (c l ), a 10pf capacitor across the series resistor will minimize pulse width distortion of an average unit. when parallel digital signals are to be isolated, propagation delay skew (t psk ) becomes important. it is defined as the absolute value of the difference between the maximum and minimum propagation delays (i.e. the worse of ?? t plh or ? t phl ) for any group of optical isolator channels operating under the same conditions. for the cpc5002, the delay t plh has a wider variation with differing optical current transfer ratios than the delay t phl . additionally, t plh will exhibit variation due to r pu and c l differences between channels. if one channel is to be used as a clock and another for data, it is recommended to use the cpc5002 output falling edge to latch the data as this edge will exhibit less channel-to-channel or part-to-part timing variation and thus will reduce worst case timing skew. in general the current transfer ratio matching between the two channels in a single cpc5002 is better than the ratio matching between multiple parts. thus the channel to channel skew for two signals isolated through the same cpc5002 will be statistically better than skew measured between signals isolated through multiple parts.
i ntegrated c ircuits d ivision cpc5002 r01 www.ixysic.com 9 3.3 output drivers designed specifically for data and clock busses, the output drivers have been configured for optimal performance and behavior. to reduce rf emissions and ringing on the output lines the active low output drivers are slew limited. in addition to limiting emissions, the slew limited outputs reduce the need for external output series resistors. whenever the outputs are in the deasserted logic high state, the open-drain outputs exhibit low leakage performance while presenting a high impedance (hi-z) to the load. additionally, during power-up and with the loss of v dd , the outputs default to the hi-z deasserted state thereby ensuring signal integrity of any bussed, open-drain signals connected to the output pins to maximize system design flexibility, the outputs are tolerant of pull-up voltages greater than the cpc5002 supply voltage, v dd , provided the pull-up voltage remains within the output?s specified voltage limits. for example, using a 3.3v supply to power the cpc5002, it?s outputs may be safely operated into a pull up resistor to a supply voltage of 6.5v. 3.4 power supply decoupling and noise reduction there are no special power supply decoupling requirements for the cpc5002. in addition, since the cpc 5002 uses optical coupling to transfer information across the barrier, no internal clocking circuits are utilized to maintain the proper output state. this negates the need to implement the required special layout or noise reduction techniques necessary to maintain emi or rfi compliance. 4 circuit examples 4.1 inverting and non-inverting configurations shown below are typical inverting and non-inverting circuit examples with the optional feed forward capacitors used for high speed signals. these designs assume a combined voltage drop of 3.3v across the input re sistor and the led with a nominal input current of 1.5ma. figure 1. inverting configuration c fwd increases instantaneous i f at led turn-on to reduce t phl at v out . figure 2. non-inverting configuration for applications where the nominal total voltage drop across the input resistor and the led is not 3.3v it will be necessary to adjust the input resistor?s value. examples of this would be different pull-up voltage supplies and v in sources that do not drive completely to the supply rails. r pu 499 3.3v v in c fwd 10pf v out 1.4k 1/2 cpc5002 in v erting: v in to v out c l 20pf 3.3v v in v out 1.4k 1/2 cpc5002 non-in v erting: v in to v out v+ r pu 499 c fwd 10pf c l 20pf
i ntegrated c ircuits d ivision 10 www.ixysic.com r01 cpc5002 4.2 application example shown below is an example of an isolated poe controller smbus where the sda signal has been split into separate sda in and sd out signals on the isolated slave side of the barrier. in this example, the low power smbus master, not shown, requires a buffer (u3) capable of driving the cpc5002 input leds. although selection of the appropriate buffer is determined by the product definition and the ability to drive the led?s, it is recommended the buffer have schmitt trigger inputs to ensure clean bounce-free led drive signals. a high power smbus master with the ability to sink 4ma of pullup current may not require a buffer to driv e the cpc5002 inputs. in this example, the poe controllers are specified as smbus high power and i 2 c compatible. this enables the poe controllers to drive the cpc5002 leds directly without the need of an external buffer. circuit design of the smbus physical layer using the cp c5002 consists of two parts, one being the led input drive current and the other being the buffered galv anically isolated logi c output signals. the following design constraints are assumed for this example: ? supply voltages: v ddx = 3.0v to 3.6v ? ambient temperature: t a = 0c to 70c ? v ol ? 0.4v for u3 and the poe controllers ? i ol ? 4ma for u3 and the poe controllers ? resistors: ? tolerance = 1% ? temperature coefficient = 100ppm figure 3. optically isolated smbus for poe controllers with separate sda in and sda out pins to minimize pulse width distortion of the output signal, the input led drive current needs to be set at the lower end of it?s operational range. because the forward voltage of the led has a negative temperature coefficient this will occur at the minimum operating temperature point wi th the minimum supply voltage. with v dd = 3.0v and v f = 1.442v at t a = 0c and i f = 1.4ma, the calculated maximum value for the series input resistor r s is 826.8 ? . taking tolerance and value change due to temperature into account, the nearest e96 standard value sets r s = 806 ? . using v ol_nominal = 0.25v and v ol_minimum = 0.1v and calculating for the led current range over the specified operating conditions with r s = 806 ? , the led input current i f will be 1.455ma to 3.212ma. at nominal operating conditions with t a = 25c, the nominal led input current is: i f_nominal = 2.28ma. scl m sda m int m scl sda in sda out smbus poe controllers 1 2 3 4 8 7 6 5 cpc5002 3.3v dds 3.3v dds 3.3v dds 3.3v dds gnd m gnd s 3.3v ddm 3.3v ddm 3.3v ddm 1 2 3 4 8 7 6 5 cpc5002 r1 806 3.3v ddm 3.3v ddm gnd s gnd m 3.3v dds 3.3v dds 3.3v dds 3.3v dds 0.1f 0.1f 0.1f 0.1f 3.3v ddm u3 u1 r2 806 u2 r3 806 r4 806 r9* r10* int scl sda in sda out int r9 and r10 are not requ ired for this design. see text for explanation. * r6 511 r5 511 r7 10k r8 10k
i ntegrated c ircuits d ivision cpc5002 r01 www.ixysic.com 11 for the outputs, the cpc5002 is compatible with both smbus and fast-mode i 2 c compatible devices. as with all mixed type devices on a bus, the weakest driver on that bus determines the minimum value of the pullup resistor. when the cpc5002 is the only device dr iving the bus as shown with u1, t he minimum e96 standard value for pullup resistors r5 and r6 will be 511 ? . for bus loading up to 400pf, this pullup resistor value will provide for fast-mode compliant i 2 c bus speeds. at lower data rates or with less capacit ive bus loading, the actual resistor value selected can be higher. when the cpc5002 shares a bus with another device as is t he case with u2, the weakest driver sets the conditions for selecting the correct resistor value. as stated earli er, the smbus master is rated as a low-power device and therefore is only capable of sinking 350ua to an output low voltage level of 0.4v. a pullup resistor attached to the maximum supply voltage level of 3.6v and pulled down by this low power driver limits the minimum pullup resistor value to 9.14k ? . after considering tolerance and temperature effects the nearest e96 standard value is 9.31k ? . most applications will typically select the more common 10k ? value for r7 and r8, which allows for a 5% resistor tolerance. although shown but not needed in this example are pullup resistors r9 and r10. these resistors, not needed by the cpc5002 at u2, are utilized whenever the busses they are attached to are also connected to device(s) having logic level inputs. with heavy loading or excessive leakage on the bus the resistors provide supplementary bias to improve pullup transition performance and to increase the output logic high level without impacting the led input current bias level. the cpc5002 can be utilized to provide digital isolated buff ering in a variety of unique applications. design support is available by contacting ixys integr ated circuits divisi on?s applications.
i ntegrated c ircuits d ivision 12 www.ixysic.com r01 cpc5002 5 manufacturing information 5.1 moisture sensitivity all plastic encapsulated semiconductor packages are susc eptible to moisture ingression. ixys integrated circuits division clas sified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, ipc/jedec j-std-020 , in force at the time of product evaluation. we test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. failure to adhere to the warnings or limitations as establ ished by the listed specificati ons could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. this product carries a moisture sensitivity level (msl) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard ipc/jedec j-std-033 . 5.2 esd sensitivity this product is esd sensitive , and should be handled according to the industry standard jesd-625 . 5.3 reflow profile this product has a maximum body temperature and time rating as shown below. all other guidelines of j-std-020 must be observed. 5.4 board wash ixys integrated circuits division recommends the use of no-clean flux formulations. however, board washing to remove flux residue is acceptable. since ixys integrated ci rcuits division employs the us e of silicone coating as an optical waveguide in many of its optically isolated products, the use of a short drying bake may be necessary if a wash is used after solder reflow processes. chlorine-based or fluorine-based solvents or fluxes should not be used. cleaning methods that employ ul trasonic energy should not be used. device moisture sensitivity level (msl) rating CPC5002G / CPC5002Gs msl 1 device maximum temperature x time CPC5002G / CPC5002Gs 250c for 30 seconds rohs 2002/95/ec e 3 pb
i ntegrated c ircuits d ivision cpc5002 r01 www.ixysic.com 13 5.5 mechanical information 5.5.1 8-pin dip package 5.5.2 8-pin surface mount package dimensions mm (inches) pcb hole pattern 2.540 0.127 (0.100 0.005) 6.350 0.127 (0.250 0.005) 9.144 0.508 (0.360 0.020) 0.457 0.076 (0.018 0.003) 9.652 0.381 (0.380 0.015) 7.239 typ. (0.285) 7.620 0.254 (0.300 0.010) 4.064 typ (0.160) 0.889 0.102 (0.035 0.004) 8-0.800 dia. (8-0.031 dia.) 2.540 0.127 (0.100 0.005) 7.620 0.127 (0.300 0.005) 7.620 0.127 (0.300 0.005) 6.350 0.127 (0.250 0.005) 3.302 0.051 (0.130 0.002) 0.254 typ (0.01) pin 1 dimensions mm (inches) pcb land pattern 2.540 0.127 (0.100 0.005) 9.652 0.381 (0.380 0.015) 6.350 0.127 (0.250 0.005) 9.525 0.254 (0.375 0.010) 0.457 0.076 (0.018 0.003) 0.813 0.120 (0.032 0.004) 4.445 0.127 (0.175 0.005) 7.620 0.254 (0.300 0.010) 0.635 0.127 (0.025 0.005) 0.254 0.127 (0.010 0.0005) 2.54 (0.10) 8.90 (0.3503) 1.65 (0.0649) 0.65 (0.0255) 3.302 0.051 (0.130 0.002) pin 1
i ntegrated c ircuits d ivision 14 www.ixysic.com r01 cpc5002 5.5.3 tape & reel packaging dimensions mm (inches) user direction of feed notes: 1. dimensions carry tolerances of eia standard 4 81-2 2. tape complies w ith all ? n otes? for constant dimensions listed on page 5 of eia-481-2 embossment emb ossed carrier top co v er tape thickness 0.102 max. (0.004 max.) 330.2 dia. (13.00 dia.) k 1 =4.20 (0.165) 0 k =4.90 (0.193) p=12.00 (0.472) w=16.00 (0.63) bo=10.30 (0.406) ao=10.30 (0.406) for additional information please vi sit our website at: www.ixysic.com ixys integrated circuits division makes no representations or wa rranties with respect to the a ccuracy or completeness of the co ntents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. neither circuit patent licenses nor indemnity ar e expressed or implied. except as set forth in ixys integrated circuits division?s standard terms and condit ions of sale, ixys integrated circuits division assumes no liability whatsoever, a nd disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringem ent of any intellectual property right. the products described in this document are not designed, intended, authorized or warranted for use as components in systems in tended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of ixys integrated circuits division?s product may resul t in direct physical harm, injury, or death to a person or severe property or environmental damage. ixys integrated circuits divisi on reserves the right to discontinue or make changes to its pr oducts at any time without notice. specification: ds-cpc5002-r01 ?copyright 2012, ixys integrated circuits division all rights reserved. printed in usa. 5/8/2012

▲Up To Search▲

Price & Availability of CPC5002G

	To Download CPC5002G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .